Unintelligble
Cool concept, but unable to use as the directions are intelligible and there are no examples. It appears the ‘help file” was translated via computer. Unable to figure out how to create and simulate file or to export verilog. UI needs work.
Has potential to be useful if author provided genuine English translation with tutorial and sample templates. I would love to try an updated version that addresses my concerns.
Has potential to be useful if author provided genuine English translation with tutorial and sample templates. I would love to try an updated version that addresses my concerns.
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Export Verilog file seems not working
Very interesting app. I’m trying to understand how it works, but it seems that clicking the export Verilog buttons doesn’t do anything.
